Current cache coherency protocols, for example, the MESI protocol, can be used to maintain cache coherency in single processor as well as multiprocessor (or multi-node) systems. However, in order to function properly, a non-bus-based multiprocessor system, e.g., a point-to-point interconnection of multiple processors, is configured to operate with a fixed number of processors or nodes. The maximum number of processors is known by a system designer prior to implementation of the system and the system is designed to support configurations up to that maximum number of nodes.
If a non-bus-based multiprocessor system is to be implemented using a greater number of processors than the maximum, the system must be redesigned. Processors cannot simply be added to the system because current cache coherency protocols specify required information whose size is dependent on the maximum number of nodes a system can have.
Because traditional cache coherency protocols are rigid and require specific designs up to a maximum configuration, these protocols increase the cost and complexity of providing systems with differing maximum numbers of processors and/or multiple configurations. For example, the IEEE Futurebus+architecture specifies a copy-back coherency protocol based on MESI and supports complex systems. FIG. 1 is a block diagram of a prior art Futurebus+architecture. The Futurebus+architecture is described in IEEE Standard 896.1 (published in 1994) and related documents.
Buses 15, 30 and 35 conform to the Futurebus+standard and are coupled to cache memories (e.g., 22, 24, 40, 45, 50, 55), to cache agents (e.g., 20, 26) or to memory agents (e.g., 21, 27). Memory agent 21 receives read and write commands from bus 30 and responds to the commands by operating with cache agent 20 as though the memory agent 21 were a main memory. Memory agent 21 tracks memory locations and cache memories 40 and 45, which are coupled to bus 30. Memory agent 27, cache agent 26, bus 35 and cache memories 50 and 55 operate in a similar manner.
Cache agent 20 provides an interface between memory agent 21 and bus 15 to provide bus snooping services for cache memories 40 and 45. Cache agent 26 operates similarly for cache memories 50 and 55. Processors 23, 25, 42, 47, 52 and 57 are coupled with cache memories 22, 24, 40, 40, 50 and 55, respectively. The processors interact with the cache memories in any manner known in the art.                Multiple levels of cache hierarchy can be provided in a similar manner with additional levels of buses and associated cache agents and memory agents. However, information fields in the cache coherency messages sent between the agents assume a fixed maximum number. This adds inefficiencies in message transmissions when the multiprocessor configuration is small relative to the maximum number. Moreover, the designers of the cache coherency protocol need to accommodate a maximum number of nodes in the system that may be larger than system designers would ever build.        